Fast serial buses defined in world standards IEEE 1394-1995 are employed for fast transfer of a large amount of data between computers, digital cameras, digital video cameras and other various home electrical devices. According to IEEE 1394-1995, data is transmitted bidirectionally over four electrical signal lines formed of two twisted-pairs.
In the p1394b conference, transmission methods using two optical fibers have been discussed.
In this method, arbitration of a token or transmission right is performed by exchanging control signals between devices in a mode that is, although not completely a full-duplex, but considered to be a pseudo full-duplex, and the data transfer is performed in a half-duplex mode using the token thus arbitrated. For example, according to IEEE 1394-1995, high and low signals are transmitted from the both devices using all the four signal lines, and the transmission right is arbitrated based on combinations of resultant potentials appearing on the signal lines.
A system for transmitting a signal of IEEE 1394 through a single optical fiber has been developed. If a single optical fiber is used in the full-duplex mode, the communication will be difficult because of the large interference, jitter and others in the transmitted signals and therefore, it is necessary to use media, that do not diffuse the light. In the case of the full-duplex mode, a photodiode which is a light receiver is located near an LED (Laser Emitting Diode) which is a source of light so that reflection of light by a coupler or the like may adversely affect a light receiving performance of the photodiode. Further, due to the full-duplexing, both the reflection on the one side and the reflection on the opposite side occur in the same medium, which complicates the processing. For these problems, a large cost is required for achieving the full-duplexing using only one optical fiber. In the case of using only one optical fiber, it is preferable to employ the half-duplexing, in which the two sides alternately perform the transmission.
A ping-pong transmission system (officially, “Time Compression Multiplexing system”) is one of such systems. According to the ping-pong transmission system, sending and receiving of a predetermined amount of data are repeated in a predetermined cycle, which will be referred to as a “ping-pong cycle” hereinafter.
According to IEEE 1394, exchange of control signals is performed in addition to data transfer. Since the control signal reflects the states of both the sides per participating in the communication, it is necessary to perform the exchange as quickly as possible. Meanwhile, it is necessary to send as large an amount of the data as possible at a time for sending the data as fast as possible. Therefore, it is preferable to continue each transfer operation for a long period so that data can be continuously transferred in one direction during the data transfer period, and it is also preferable to reduce a transfer period other than the data transfer so that control signals may be exchanged fast. Thus, there has been devised and used an improved ping-pong transmission system that switches the operation between the short fixed length transmission, which requires a short period per operation, and the variable length transmission, which allows increase in transfer period per operation, if necessary. In this specification, this method is called a “variable-burst-length ping-pong transmission system”.
In the transmission system using the optical fiber, only the send-code is sent in one direction at a time, and the clock signal is not sent. On the receiver side, it is necessary to recover the clock from the received code. For recovering the clock, it is not preferable if a continuation of “1” or “0” larger than a certain length is present in the send-code. This is because recovery of the clock signal needs transitions in signal level of the received code occurring with a certain frequency. In general, therefore, encoding is performed by superimposing a clock on the send-code so that the transitions in signal level will occur with a certain frequency.
A system called “4B5B” and a system called “8B10B” have been known in the art of superimposing the clock on the send-code. In the 4B5B encoding system, four bits of the send-data are encoded into five bits. In the system called 8B10B, eight bits of the send-data are encoded into 10 bits. In the encoded send-code, transitions in signal level will occur with a certain frequency so that the clock signal can be recovered on the receiver side.
According to p1394b, the 8B10B encoding system described above is employed. Send data is sent as a packet, and a header of a fixed length is added to the leading end thereof for indicating that a packet proper follows. A bit pattern of the header is a specific bit string called a “synchronous pattern”. By detecting this specific bit string on the receiver side, it is possible to know that the packet proper follows, and it is also possible to recover a clock signal based on this specific bit string, and thereafter to use the clock signal thus recovered for receiving the code. If this encoding system is applied to the ping-pong transmission system of a variable burst length described above, a portion of the packet except for the header is formed of a set of codes, each of which is formed of 10 bits, which is the shortest code length.
In the ping-pong transmission system of the variable burst length type, it is necessary to determine whether the packet has a fixed length or a variable length. In a typical method for this determination, a bit for determination is arranged at the header of the packet. However, if only the control codes are transmitted with a fixed length, and if the data codes are always transmitted with a variable length, as in the ping-pong transmission system of the variable burst length type, i.e., if only a relatively few kinds of codes are transmitted with a fixed length, a special code may be defined for indicating that a variable length packet follows, it is possible to determine whether the packet has a fixed length or a variable length. An example of such a packet format is shown in FIG. 2.
Referring to FIG. 2(A), a data code packet 500 includes a header 502 having a specific bit string as described before, a data start code 504 of 10 bits indicating that data follows, data 516 which is a data proper to be sent, and a data end code 514 of 10 bits indicating the end of data. Data 516 includes one or more data codes 506, 508, . . . and 512 each formed of 10 bits.
Referring to FIG. 2(B), a control code packet 530 includes a header 532, which is the same as header 502, and a control code 534 of 10 bits.
When data code packet 500 is to be transmitted, data start code 504 is inserted immediately after header 502 and before data 516, and data end code 514 is added immediately after data 516. When equipment on a receiver side receives data start code 504, it expects coming of data 516, and performs decoding of the data and other processing. When data end code 514 is received during data reception, the equipment on the receiver side knows the end of data code packet 500, and changes the modes in order to receive control code packet 530 of a normal fixed length.
In the conventional method, therefore, the packet is handled as a variable length packet only when the leading 10 bits of the packet immediately after the header 502 is the data start code.
Particularly, according to IEEE 1394, a DATA—PREFIX code is attached before the data, and a DATA—PREFIX code or a DATA—END code is appended after the data. Therefore, the above system is suitable for IEEE 1394.
Referring to FIG. 1, description will now be given on a conventional device, which uses the packet structure shown in FIG. 2, and achieves the ping-pong transmission for transmitting the data code encoded in the 8B10B encoding method as well as the control code of 10 bits.
Referring to FIG. 1, a conventional transmitting device 400 has two kinds of internal clock signals, and more specifically has a fast clock signal CLK250 having a frequency, e.g., of 250 MHz for handling serial data and a clock signal CLK25, which has a frequency 25 MHz and a period ten times larger than that of clock signal CLK250, for handling parallel data of 10 bits.
Transmitting device 400 includes: an optical fiber interface 102 connected to a transmission path 101, which is formed of one optical fiber and is connected to equipment on the opposite side; a bit synchronizing circuit 103 connected to optical fiber interface 102 for outputting the signal received from transmission path 101 via optical fiber interface 102, in synchronization with clock signal CLK250; a character synchronizing circuit 404 for receiving the output of bit synchronizing circuit 103 and clock signal CLK25, finding header 502 in the bit string output from bit synchronizing circuit 103, preparing characters each formed of 10 bits from the bit string following header 502, and outputting the characters thus prepared in synchronization with internal clock signal CLK25; an 8B10B decoder 109 for receiving the output of character synchronizing circuit 404 and clock signal CLK25, decoding the characters encoded in the 8B10B encoding method, and restoring the original data from the sent code for outputting the same; and an internal interface 113 (i.e., an interface for internal circuits of the equipment) for internally applying data received from 8B10B decoder 109, and applying data to be externally output from the equipment and the internal state of the equipment to transmitting device 400. Note that the “equipment” here indicates an upper layer(s) in a layer structure of communication in many cases.
Optical fiber interface 102 has a receiver (not shown) for receiving via transmission path 101 the bit string sent from the equipment on the other side, and applying the same to bit synchronizing circuit 103, and a driver (not shown) for driving onto transmission path 101 the bit string to be sent from transmission device 400 to transmission path 101.
Transmission device 400 further includes a control portion 405 which operates in synchronization with clock signal CLK25, receives the control code existing in the character string output from character synchronizing circuit 404 as well as the data output from the equipment via internal interface 113 and the internal state of the equipment, and controls based on them various portions of transmission device 400 and, if necessary, the internal portions of the equipment (via interface 113) for receiving and sending. Transmission device 400 further includes an 8B10B encoder 110 which operates under control of control portion 405 to superimpose the clock information on the original data of 8 bits applied from internal interface 113 into the equipment using the 8B10B encoding method for outputting the code of 10 bits, an FIFO memory 410 which is provided at the output of 8B10B encoder 110 for matching the output timing of data from 8B10B encoder 110 with the timing allowing transmission onto transmission path 101, a packet producing circuit 406 which has a parallel output of 10 bits in width, and is connected to the output of FIFO memory 410 for adding headers 502 and 532 to codes to be sent to the equipment on the opposite side in accordance with the signal received from control portion 405, and thereby producing data packets in accordance with the format shown in FIG. 2, and a parallel-serial converting circuit 407 which receives the output of packet producing circuit 406 and clock signal CLK250, converts the parallel signals formed of character units each formed of 10 bits and sent from packet producing circuit 406 into serial bit strings, and applying the same to optical fiber interface 102.
In the case where control portion 405 controls the timing of output of data from the equipment, FIFO memory 410 may not be required.
Description will now be given on the control of transmission device 400 by control portion 405 during the data receiving and sending. During data reception, control portion 405 determines whether the code sent from character synchronizing circuit 404 matches with any one of the control codes or not. If it matches with any one of the control codes, control portion 405 controls timing of production and sending of the send-control code as well as an internal operation of the equipment in accordance with the matching code. Control portion 405 also determines whether the data packet is being received, or the control packet is being received.
During the sending, control portion 405 determines the contents of the packet to be sent to the equipment on the opposite side as well as the timing of such sending based on the receive-control code, the internal state of the equipment received via internal interface 113, and others. For this purpose, control portion 405 has a function of determining the control code to be sent to the packet producing circuit as well as a function of producing a send-enable signal for instructing the packet producing circuit whether the sending is to be performed or not.
Referring to FIGS. 1 and 2 as well as a timing chart shown in FIG. 3, description will now be given on a manner, in which conventional transmission device 400 performs the ping-pong transmission. First, transmission device 400 operates as follows after it receives the control packet from the equipment on the opposite side and before it sends the control packet to the equipment on the opposite side.
It is now assumed that the equipment on the opposite side sends the control packet in the format shown in FIG. 2(B) to transmission device 400 via transmission path 101. In the equipment on the receiver side, optical fiber interface 102 reads the bit string on transmission path 101, and sends it to bit synchronizing circuit 103. Bit synchronizing circuit 103 synchronizes this bit string with clock signal CLK250 and, after the bit synchronization, applies it as receive-control packet 601 to character synchronizing circuit 404. As is apparent from FIGS. 3(A) and 3(B), this bit-synchronized receive-control packet 601 is not synchronized with internal clock signal (CLK250) 600.
Character synchronizing circuit 404 removes the header from bit-synchronized receive-control packet 601, and outputs the portion (i.e., control code) other than the header as a character-synchronized receive-control code 602 of a 10-bit parallel form synchronized with clock signal CLK25 shown in FIG. 3(A). Character-synchronized receive-control code 602 is applied to control portion 405 and 8B10B decoder 109.
If the received code is different from data start code 504 shown in FIG. 2(A), transmission device 400 operates as follows. If the receive-control code is not data start code 504, data 516 does not follow. For ending the reception and starting the sending operation, control portion 405 immediately outputs a send-enable signal 603 shown in FIG. 3(D) to packet producing circuit 406. At the same time, control portion 405 operates in accordance with the receive-control code, and controls the internal operation of the equipment and/or the operation of the other circuits via internal interface 113, if necessary.
Thereafter, if the control code is to be sent to the equipment on the opposite side, control portion 405 produces send-control code 604 (FIG. 3(E)), and outputs it to packet producing circuit 406 at the next rising edge of internal clock signal (CLK25) 600. When the data is to be sent to the equipment on the opposite side, control portion 405 produces a “data start” code.
When packet producing circuit 406 receives send-enable signal 603 from control portion 405, it immediately produces and outputs a header to parallel-serial converting circuit 407. As can be seen from FIGS. 3(C) and 3(D), control portion 405 sends send-control code 604 to packet producing circuit 406 in the clock cycle immediately after send-enable signal 603. Therefore, packet producing circuit 406 adds send-control code 604 to the end of the header. As a result, a send-control packet 605 shown in FIG. 3(F) is completed as a packet to be sent.
In FIG. 3(F), when send-control code 604 is the “data start” code, packet producing circuit 406 further reads data from FIFO memory 410, and outputs it to parallel-serial converting circuit 407. When FIFO memory 410 becomes empty, packet producing circuit 406 outputs a “data end” code. Accordingly, a send-data packet 606 shown in FIG. 3(G) is obtained as the packet in this stage.
Consequently, the output of the send-control code from packet producing circuit 406 of transmission device 400 is delayed from the appearance of receive-control packet 601 in the receive-control packet after the bit synchronization by a delay time, which is equal to a sum of delay times 611–614.
Although description has been given by way of example on the case of half-duplex transmission, the conventional device has the following structure in the case of the full-duplex transmission. In FIG. 4, parts and portions having functions similar to those shown in FIG. 1 bear the same reference numbers and the same names. Accordingly, description thereof is not repeated.
In the full-duplex transmission, codes are sent on a transmission path without an interruption while transmission is established. Two kinds of codes, which are a control code and a data code, are transmitted similarly to the case of the half-duplex transmission. Before transmitting the data code, DATA—PREFIX code is transmitted. When ending the operation of sending the data code, DATA—END code is sent.
In this example, there is a concept of the data token, and data is sent from a side having the data token. Therefore, the token must be passed between the one side and the other side. This passing of the data token is performed in the following manner.
Referring to FIG. 6, FIG. 6(A) shows a flow of code sent from a sending device, to which the token is to be passed. FIG. 6(B) shows a flow of codes sent from the equipment on the opposite side.
First, the equipment, which is to obtain the token, and will be referred to as a “sender side” hereinafter, sends the control code, which is called a “REQUEST code” to the other or opposite side. As shown in FIG. 6(A), this REQUEST code is repetitively sent until the sender side receives a response from the other side.
The equipment, which receives this REQUEST code, and will be referred to as a “receiver side” hereinafter, sends a control code, which is called a “GRANT” code to the sender side if it accepts the REQUEST code for passing the token to the sender side. This GRANT code is repetitively sent until the receiver side receives a response from the sender side.
When the sender side receives the GRANT code, it starts to send the send-code instead of DATA—PREFIX code to the equipment on the opposite side, and prepares for the data code sending. When the receiver side receives DATA—PREFIX code, it starts to send a control code called “IDLE”. The sender side receiving this IDLE determines that the receiver side is now ready to receive the data code, and starts sending of the data.
For receiving the data code, the receiver side must change its receiving mode from that for receiving the control code. FIG. 5 is a flowchart showing the processing performed on the receiver side for the above.
First, the receiving mode is set to the control code receiving mode (S1). After the receiving mode is set to the control code receiving mode, one character is read from the code sent from the sender side (S2). Then, the code expressed by the read character is determined (S3). When it is determined that the code is DATA—PREFIX code, the control returns to step S2, and processing in steps S2 and S3 is repeated.
When it is determined in step S3 that DATA—PREFIX code is received, the control advances to a step S4, and the receiving mode is set to the data code receiving mode. The data code sent from the sender side is read character by character (S5). In subsequent step S6, it is determined whether the code thus read is DATA—END code or not. When it is determined that DATA—END code is received, the control returns to step S1. Otherwise, the control returns to step S5, and the processing in steps S5 and S6 is repeated.
Referring to FIG. 4, a transmission device 700 performing the communication in the full-duplex mode is connected to a sending path 101A, which is a logically one transmission path and is made of an optical fiber, and is also connected to a sending path 101B of the equipment on the opposite side, which is a logically one transmission path and is made of an optical fiber, for performing the communication in the full-duplex mode with respect to the equipment on the opposite side. The other end of sending path 101A is connected to an optical receiver of the equipment on the opposite side, and the other end of sending path 101B of the equipment on the opposite side is connected to the optical transceiver of the equipment on the opposite side. However, sending path 101A and sending path 101B of the opposite equipment may be formed of two optical fibers each forming one of paths 101A and 101B, or may be formed of only one fiber. On sending path 101A, the send-code always flows from transmission device 700 to the opposite equipment, and the send-code always flows on sending path 101b of the opposite equipment from the opposite equipment.
The transmission device 700 has two internal clocks, which are clock signals CLK25 and CLK250, similarly to transmission device 400 shown in FIG. 1.
Transmission device 700 includes an optical receiver 102B connected to transmission path 101B of the opposite equipment, bit synchronizing circuit 103 receiving the output of optical receiver 102B, character synchronizing circuit 404 receiving the output of bit synchronizing circuit 103, 8B10B decoder 109 receiving the output of character synchronizing circuit 404, and internal interface 113 receiving the output of 8B10B decoder 109.
Transmission device 700 further includes a controller 705 which operates in synchronization with clock signal CLK25 to receive the control code existing in the character string sent from character synchronizing circuit 404 as well as the data sent from the inside of the equipment and the internal state of the equipment applied via internal interface 113, and further operates, based on them, to control various portions of transmission device 700 for sending and receiving, if necessary, to control the inside of the equipment via internal interface 113, and to output the selector signal and send-control code to be described later. Transmission device 700 further includes 8B10B encoder 110 which receives the data sent from internal interface 113, encodes the same in the 8B10B encoding method, and outputs the data code in batches of 10-bit parallel character, a code selector 706 which receives the output of 8B10B encoder 110 and the output of control portion 705, and is responsive to the selector signal applied from control portion 705 by selecting one of the outputs of 8B10B encoder 110 and control portion 705, and outputting the same as a 10-bit parallel signal, parallel-serial converting circuit 407 which performs parallel-serial conversion on the output of code selector 706 to output bit strings, and optical transceiver 102A which converts the send-codes output from parallel-serial converting circuit 407 into optical signals, and outputs the same onto sending path 101A.
Transmission device 700 will be described only in connection with differences from transmission device 400. Transmission device 700 operates as follows. For sending and receiving operations, control portion 705 of transmission device 700 has functions, which can be roughly classified into a function of processing the received codes and a function of selecting the send-code.
First, description will be given on the processing of the received code by control portion 70. Control portion 705 switches the receiving mode depending on the code sent from character synchronizing circuit 404. When the receiving mode is the control code receiving mode, control portion 705 reads one character in the output of character synchronizing circuit 404, and decodes it for performing necessary processing. In this case, since the output of 8B10B decoder 109 is of no importance, control portion 705 masks the output of 8B10B decoder 109, and sends to the equipment via internal interface 113 a control signal notifying the internal circuits of the equipment of the fact that the output of 8B10B decoder 109 is invalid. The equipment which received this control signal performs the processing of ignoring the output of 8B10B decoder 109 and other processing.
When it is determined that DATA—PREFIX code is received from the opposite equipment, the receiving mode is set to the data code receiving mode. Thereafter, the codes sent from the opposite side are read character by character. At this time, the output of 8B10B decoder 109 is set valid.
In the sending operation, transmission device 700 operates as follows. Control portion 705 selects the control code to be sent to the opposite equipment in accordance with the control code sent from character synchronizing circuit 404 and the state of transmission device 700. Control portion 705 applies the control code thus selected to code selector 706. Control portion 705 applies to code selector 706 the select signal for indicating whether the output of 8B10B encoder 110 is to be selected or the control code applied from control portion 705 is to be selected.
Code selector 706 selects either the data code applied from 8B10B encoder 110 or the control code applied from control portion 705 in accordance with the value of the select signal applied from control portion 705, and applies it to parallel-serial converting circuit 407.
Parallel-serial converting circuit 407 converts the data code or control code applied from code selector 706 into the bit string, and applies it to optical transceiver 102A, which converts this bit string into the optical signal, and outputs it onto sending path 101A.
According to the fast serial communication, it is desired that the foregoing exchange of control codes is performed as fast as possible. However, any one of the foregoing examples is susceptible to improvement for allowing fast exchange of the control codes. One of the reasons for it is that the control code is excessively long in any case.
Actually, there are only about ten kinds of control codes, and about five bits are enough for the control code. Thus, it is not necessary to allocate 10 bits to the control code similarly to the data code, and there is a possibility that the time required for transmission of the control code can be reduced.
Accordingly, an object of the invention is to provide a transmission device and a method, which can further reduce a length of the control code, and thereby reduce a time required for communication.
Another object of the invention is to provide a transmission device and a method, which can further reduce a length of the control code, and thereby reduce a time required for negotiation.
Still another object of the invention is to provide a transmission device and a method, which can further reduce a length of the control code, and thereby reduce a ping-pong period.